An Area and Energy Efficient Serial-Multiplier

Mohd. Tasleem Khan, Jinti Hazarika

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In this work, we present an area and energy-efficient serial multiplier. Specifically, we exploit symmetries in odd and even partial products (PPs) in its radix-γ implementation. Subsequently, we express them as ∓ (2k±1) with 1≤k≤log2γ−1, which enable to reduce the hardware resources. For γ≥16, the above representation becomes invalid, requiring additional power-of-two terms and raising hardware costs. To address this, we utilize recursive symmetries in PPs, which enable time-sharing and reduce the logic resources for efficient realization. ASIC synthesis results show the proposed design has substantial savings in area and energy than the state-of-the-art design.
Original languageEnglish
JournalIEEE Embedded Systems Letters
Early online date10 Jan 2024
Publication statusE-pub ahead of print - 10 Jan 2024


  • Adders
  • Area
  • ASIC
  • Clocks
  • Costs
  • Energy
  • Logic gates
  • Multiplexing
  • Optimization
  • Radix-γ Serial Multiplier
  • Transforms

ASJC Scopus subject areas

  • Control and Systems Engineering
  • General Computer Science


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