An alternative approach to design reconfigurable mixed signal VLSI da based FIR filter

Prateek Kumar Sharma; M. Tasleem Khan; Shaik Rafi Ahamed

doi:10.1109/TechSym.2016.7872697

An alternative approach to design reconfigurable mixed signal VLSI da based FIR filter

Prateek Kumar Sharma, M. Tasleem Khan, Shaik Rafi Ahamed

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an alternative approach to design reconfigurable mixed signal distributed arithmetic (DA) based finite impulse response (FIR) filter. The proposed architecture is based on the use of normal CMOS transistor for various computational blocks involved in the filter design. To maintain the reconfigurability, an electrically erasable programmable read only memory (EEPROM) based potentiometer (POT) is also employed that stores the analog filter weights. Moreover, the analog weights are separately added in last cycle corresponding to most significant bit and eliminates the extra control circuitry for bit-inversion. We have simulated the proposed architecture in UMC 180 nm CMOS using Cadence Spectre with input sampling frequency of 1.25 MHz. It is found that the proposed architecture dissipates the static power of 4.85 mW.

Original language	English
Title of host publication	2016 IEEE Students' Technology Symposium
Publisher	IEEE
Pages	284-288
Number of pages	5
ISBN (Electronic)	9781509051632
DOIs	https://doi.org/10.1109/TechSym.2016.7872697
Publication status	Published - 9 Mar 2017
Event	4th IEEE Students' Technology Symposium 2016 - Kharagpur, West Bengal, India Duration: 30 Sept 2016 → 2 Oct 2016

Conference

Conference	4th IEEE Students' Technology Symposium 2016
Abbreviated title	TechSym 2016
Country/Territory	India
City	Kharagpur, West Bengal
Period	30/09/16 → 2/10/16

Keywords

digital potentiometer (digPOT)
Distributed arithmetic (DA)
finite impulse response (FIR)
Floating gate (FG)
look-up table (LUT)

ASJC Scopus subject areas

Electrical and Electronic Engineering
Control and Optimization
Instrumentation
Computer Science Applications

Access to Document

10.1109/TechSym.2016.7872697

Cite this

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title = "An alternative approach to design reconfigurable mixed signal VLSI da based FIR filter",

abstract = "This paper presents an alternative approach to design reconfigurable mixed signal distributed arithmetic (DA) based finite impulse response (FIR) filter. The proposed architecture is based on the use of normal CMOS transistor for various computational blocks involved in the filter design. To maintain the reconfigurability, an electrically erasable programmable read only memory (EEPROM) based potentiometer (POT) is also employed that stores the analog filter weights. Moreover, the analog weights are separately added in last cycle corresponding to most significant bit and eliminates the extra control circuitry for bit-inversion. We have simulated the proposed architecture in UMC 180 nm CMOS using Cadence Spectre with input sampling frequency of 1.25 MHz. It is found that the proposed architecture dissipates the static power of 4.85 mW.",

keywords = "digital potentiometer (digPOT), Distributed arithmetic (DA), finite impulse response (FIR), Floating gate (FG), look-up table (LUT)",

author = "Sharma, {Prateek Kumar} and Khan, {M. Tasleem} and Ahamed, {Shaik Rafi}",

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Y1 - 2017/3/9

N2 - This paper presents an alternative approach to design reconfigurable mixed signal distributed arithmetic (DA) based finite impulse response (FIR) filter. The proposed architecture is based on the use of normal CMOS transistor for various computational blocks involved in the filter design. To maintain the reconfigurability, an electrically erasable programmable read only memory (EEPROM) based potentiometer (POT) is also employed that stores the analog filter weights. Moreover, the analog weights are separately added in last cycle corresponding to most significant bit and eliminates the extra control circuitry for bit-inversion. We have simulated the proposed architecture in UMC 180 nm CMOS using Cadence Spectre with input sampling frequency of 1.25 MHz. It is found that the proposed architecture dissipates the static power of 4.85 mW.

AB - This paper presents an alternative approach to design reconfigurable mixed signal distributed arithmetic (DA) based finite impulse response (FIR) filter. The proposed architecture is based on the use of normal CMOS transistor for various computational blocks involved in the filter design. To maintain the reconfigurability, an electrically erasable programmable read only memory (EEPROM) based potentiometer (POT) is also employed that stores the analog filter weights. Moreover, the analog weights are separately added in last cycle corresponding to most significant bit and eliminates the extra control circuitry for bit-inversion. We have simulated the proposed architecture in UMC 180 nm CMOS using Cadence Spectre with input sampling frequency of 1.25 MHz. It is found that the proposed architecture dissipates the static power of 4.85 mW.

KW - digital potentiometer (digPOT)

KW - Distributed arithmetic (DA)

KW - finite impulse response (FIR)

KW - Floating gate (FG)

KW - look-up table (LUT)

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DO - 10.1109/TechSym.2016.7872697

M3 - Conference contribution

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BT - 2016 IEEE Students' Technology Symposium

PB - IEEE

T2 - 4th IEEE Students' Technology Symposium 2016

Y2 - 30 September 2016 through 2 October 2016

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An alternative approach to design reconfigurable mixed signal VLSI da based FIR filter

Abstract

Conference

Keywords

ASJC Scopus subject areas

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