Linearizing power amplifiers (PA) using digital pre-distortion (DPD) results in the use of a pre-distorted driving input signal that exhibits higher peak-to-average power ratio (PAPR). This results in a decrease in the PA efficiency which is dependent on the level of output power back-off required. This work proposes a new linearization architecture based on a new 'post-distortion' method for power amplifier (PA) nonlinearity compensation. The proposed architecture allows for PA linearization with optimal input signal drive level to avoid efficiency degradation. A pseudomorphic high electron-mobility transistor (pHEMT) dual input PA architecture is also introduced and shown to be suitable for the proposed linearization approach. In comparison to classic pre-distortion techniques, the proposed post-distortion improves the output power by 2 dB and the drain efficiency by 9% in the presence of a 20MHz LTE up-link signal.
- power amplifier
- stacked architecture