A throughput maximised parallel architecture for 2D fast Discrete Pascal Transform

M. M. Wong, M. L. Dennis Wong*, I. Hijazin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


In this paper, we present a fully pipelined parallel implementation of a two dimensional (2D) Discrete Pascal Transform (DPT). Our approach first makes use of the properties of the Kronecker product and the vec operation on matrices to form an alternate 2D DPT representation suitable for column parallel computation. Next, we lend ourselves to the results from Skodras' work in 1D DPT to achieve the final architecture for fast 2D DPT. With a fully pipelined implementation, the architecture possesses an initial latency of 2 (N - 1) clock cycles and a maximum throughput of one complete two dimensional transform every clock cycle, given any input matrix of size N × N. To evaluate our work, our results obtained from actual FPGA implementation were benchmarked against results from other previous works.

Original languageEnglish
Pages (from-to)585-591
Number of pages7
JournalComputers and Electrical Engineering
Issue number3
Publication statusPublished - May 2010


  • Fast transform
  • Parallel architecture
  • Pascal matrix
  • Polynomial transform

ASJC Scopus subject areas

  • Computer Science(all)
  • Electrical and Electronic Engineering
  • Control and Systems Engineering


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