Abstract
This article presents a novel time-shared and lookup table (LUT)-less pipelined architecture for a least-mean-square (LMS) adaptive filter (ADF). The proposed approach first employs a time-shared architecture for the pipelined LMS ADF to compute each filter partial product and coefficient increment term using a single multiplier. Critical path analysis of this architecture is carried out to determine the pipeline requirements. Next, a novel LUT-less multiplier is suggested by exploiting the symmetries between the odd-multiples. Due to the symmetries between the odd-multiples, offset terms are added using an adder tree. For higher wordlength coefficients, only a few adders are required to generate the odd-multiples, and only one offset adder tree is required. Finally, a novel super-latch is developed to pipeline the LUT-less multiplier with adaptation delays of the pipelined LMS ADF. From the implementation results, it is found that the proposed design for the 32nd-order filter occupies 60.32% less area, consumes 61.93% less power, and utilizes 58.83% less sliced LUTs and 63.28% fewer flip-flops over the best existing design.
Original language | English |
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Pages (from-to) | 188-197 |
Number of pages | 10 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 28 |
Issue number | 1 |
DOIs | |
Publication status | Published - Jan 2020 |
Keywords
- Adaptive filter (ADF)
- finite impulse response (FIR)
- least mean square (LMS)
- delays
- Finite impulse response filters
- adders
- Table lookup
- pipelines
- complexity theory
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering