Logic optimization over the logic basis (AND, XOR, NOT) has received increased attention in recent works due to the potential in low gate count logic circuit implementation. Previous logic minimization heuristic in this logic basis involved randomized selection processes and thus exhibits uncontrolled variations in the results produced and algorithm execution time. In this work, we demonstrate a novel approach to the same problem using Positive Polarity Reed-Muller factorization. The proposed algorithm eliminates the reliance on randomness and produces all optimal solutions obtainable through the factorization method. This enables the application of different selection criteria post-optimization to maximize circuit sharing between functions. The proposed algorithm is aimed towards optimizing the S-boxes of lightweight cryptographic schemes.