A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

Antony Xavier Glittas; Mathini Sellathurai; Gopalakrishnan Lakshminarayanan

doi:10.1109/TVLSI.2015.2504391

A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

Antony Xavier Glittas, Mathini Sellathurai, Gopalakrishnan Lakshminarayanan

Research output: Contribution to journal › Article › peer-review

41 Citations (Scopus)

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Abstract

Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an N/2-point decimation in time FFT and an N/2-point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput.

Original language	English
Pages (from-to)	2402-2406
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	24
Issue number	6
Early online date	6 Jan 2016
DOIs	https://doi.org/10.1109/TVLSI.2015.2504391
Publication status	Published - Jun 2016

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture
Software

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@article{a9fe6293996a4e4ab75a5325892a953a,

title = "A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO",

abstract = "Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an N/2-point decimation in time FFT and an N/2-point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput.",

author = "Glittas, {Antony Xavier} and Mathini Sellathurai and Gopalakrishnan Lakshminarayanan",

year = "2016",

month = jun,

doi = "10.1109/TVLSI.2015.2504391",

language = "English",

volume = "24",

pages = "2402--2406",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "IEEE",

number = "6",

}

TY - JOUR

T1 - A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

AU - Glittas, Antony Xavier

AU - Sellathurai, Mathini

AU - Lakshminarayanan, Gopalakrishnan

PY - 2016/6

Y1 - 2016/6

N2 - Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an N/2-point decimation in time FFT and an N/2-point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput.

AB - Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an N/2-point decimation in time FFT and an N/2-point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput.

UR - http://www.scopus.com/inward/record.url?scp=84953212041&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2015.2504391

DO - 10.1109/TVLSI.2015.2504391

M3 - Article

AN - SCOPUS:84953212041

SN - 1063-8210

VL - 24

SP - 2402

EP - 2406

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 6

ER -

A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

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