A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

Antony Xavier Glittas, Mathini Sellathurai, Gopalakrishnan Lakshminarayanan

Research output: Contribution to journalArticle

17 Citations (Scopus)
190 Downloads (Pure)

Abstract

Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an N/2-point decimation in time FFT and an N/2-point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput.

Original languageEnglish
Pages (from-to)2402-2406
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number6
Early online date6 Jan 2016
DOIs
Publication statusPublished - Jun 2016

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

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