Abstract
In this work, our aim is to achieve a high throughput compact AES S-box with minimal power consumption. In most VLSI implementations, there exist a definite trade off between hardware performance and its operating requirements. In this work, we propose a novel pipelining arrangement over the compact composite field AES S-box such that both high throughput and low power are optimized. Our S-box outperformed the conventional pipelined AES S-box from three perspectives, (i) the most optimum (compact and short critical path) composite field AES S-box is used, which has different arithmetic properties compared to previous works; (ii) Algebraic Normal Form (ANF) representation is utilized to induce consistent and optimal pipelining arrangement; and (iii) Fine-grain pipelining is applied in the GF (24) multiplier. As such, a higher throughput rate is attained and at the same time the dynamic hazards is mitigated. A high throughput of 3.3Gbps with a low power consumption of 34.98mW and total of 95 LE (Logic Element) composite field AES S-box is reported in this work.
Original language | English |
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Title of host publication | Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010 |
Pages | 318-323 |
Number of pages | 6 |
DOIs | |
Publication status | Published - 2010 |
Event | 2nd Asia Symposium on Quality Electronic Design 2010 - Penang, Malaysia Duration: 3 Aug 2010 → 4 Aug 2010 |
Conference
Conference | 2nd Asia Symposium on Quality Electronic Design 2010 |
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Abbreviated title | ASQED 2010 |
Country/Territory | Malaysia |
City | Penang |
Period | 3/08/10 → 4/08/10 |
Keywords
- Advanced Encryption Standard (AES) S-box
- Algebraic Normal Form (ANF)
- Composite field arithmetic (CFA)
- Low power
- Pipeline
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality