This article presents a bandwidth extended digital predistortion system suitable for LTE-advanced applications. The proposed predistortion system uses a two-box architecture based on the cascade of a memory polynomial followed by a memoryless predistortion function. The memoryless predistorter is identified offline and used to perform a coarse linearization which cancels out most of the static nonlinearity of the device under test allowing for a reduced observation bandwidth for the synthesis of the memory polynomial predistortion sub-function. The proposed predistorter was experimentally validated and its performance benchmarked against a predistorter having the same structure but identified using the conventional approach. The measurement results demonstrate that the proposed predistorter requires 30% less sampling speed for the analog to digital converter of the feedback path.
|Number of pages||9|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - Dec 2014|