TY - GEN
T1 - 5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager
AU - Henderson, Robert K.
AU - Johnston, Nick
AU - Hutchings, Sam W.
AU - Gyongy, Istvan
AU - Abbas, Tarek Al
AU - Dutton, Neale
AU - Tyler, Max
AU - Chan, Susan
AU - Leach, Jonathan
PY - 2019/3/7
Y1 - 2019/3/7
N2 - Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to laser returns affected by the inverse square law over 2-3 decades of distance, diverse target reflectivity, and high solar background [1]. Integrated CMOS SPADs have a native DR exceeding 140dB, typically extending from the noise floor of few cps to 100's Mcps peak rate. To deliver this DR to downstream DSP, large SPAD time-resolved imaging arrays must count and time billions of single photon events per second demanding massively parallel on-chip pixel processing to achieve practical I/O power consumption and data rates. Hybrid Cu-Cu bonding offers a mass-manufacturable platform to implement these sensors by providing high-fill-factor SPADs optimised for NIR stacked on dense nanoscale digital processors [2]. Stacked sensor architectures involving pixel-level histogramming, on-chip peak detection and TDC/processor resource sharing are now being investigated [3-5].
AB - Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to laser returns affected by the inverse square law over 2-3 decades of distance, diverse target reflectivity, and high solar background [1]. Integrated CMOS SPADs have a native DR exceeding 140dB, typically extending from the noise floor of few cps to 100's Mcps peak rate. To deliver this DR to downstream DSP, large SPAD time-resolved imaging arrays must count and time billions of single photon events per second demanding massively parallel on-chip pixel processing to achieve practical I/O power consumption and data rates. Hybrid Cu-Cu bonding offers a mass-manufacturable platform to implement these sensors by providing high-fill-factor SPADs optimised for NIR stacked on dense nanoscale digital processors [2]. Stacked sensor architectures involving pixel-level histogramming, on-chip peak detection and TDC/processor resource sharing are now being investigated [3-5].
UR - http://www.scopus.com/inward/record.url?scp=85063533714&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2019.8662355
DO - 10.1109/ISSCC.2019.8662355
M3 - Conference contribution
AN - SCOPUS:85063533714
T3 - International Solid- State Circuits Conference (ISSCC)
SP - 106
EP - 108
BT - 2019 IEEE International Solid-State Circuits Conference (ISSCC)
PB - IEEE
T2 - 2019 IEEE International Solid-State Circuits Conference
Y2 - 17 February 2019 through 21 February 2019
ER -