5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager

Robert K. Henderson, Nick Johnston, Sam W. Hutchings, Istvan Gyongy, Tarek Al Abbas, Neale Dutton, Max Tyler, Susan Chan, Jonathan Leach

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to laser returns affected by the inverse square law over 2-3 decades of distance, diverse target reflectivity, and high solar background [1]. Integrated CMOS SPADs have a native DR exceeding 140dB, typically extending from the noise floor of few cps to 100's Mcps peak rate. To deliver this DR to downstream DSP, large SPAD time-resolved imaging arrays must count and time billions of single photon events per second demanding massively parallel on-chip pixel processing to achieve practical I/O power consumption and data rates. Hybrid Cu-Cu bonding offers a mass-manufacturable platform to implement these sensors by providing high-fill-factor SPADs optimised for NIR stacked on dense nanoscale digital processors [2]. Stacked sensor architectures involving pixel-level histogramming, on-chip peak detection and TDC/processor resource sharing are now being investigated [3-5].

LanguageEnglish
Title of host publication2019 IEEE International Solid-State Circuits Conference (ISSCC)
PublisherIEEE
Pages106-108
Number of pages3
ISBN (Electronic)9781538685310
DOIs
Publication statusPublished - 7 Mar 2019
Event2019 IEEE International Solid-State Circuits Conference - San Francisco, United States
Duration: 17 Feb 201921 Feb 2019

Publication series

NameInternational Solid- State Circuits Conference (ISSCC)
PublisherIEEE
ISSN (Electronic)2376-8606

Conference

Conference2019 IEEE International Solid-State Circuits Conference
Abbreviated titleISSCC 2019
CountryUnited States
CitySan Francisco
Period17/02/1921/02/19

Fingerprint

Image sensors
Pixels
Sensors
Electric power utilization
Photons
Imaging techniques
Lasers
Processing
SPAD

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Henderson, R. K., Johnston, N., Hutchings, S. W., Gyongy, I., Abbas, T. A., Dutton, N., ... Leach, J. (2019). 5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager. In 2019 IEEE International Solid-State Circuits Conference (ISSCC) (pp. 106-108). (International Solid- State Circuits Conference (ISSCC)). IEEE. https://doi.org/10.1109/ISSCC.2019.8662355
Henderson, Robert K. ; Johnston, Nick ; Hutchings, Sam W. ; Gyongy, Istvan ; Abbas, Tarek Al ; Dutton, Neale ; Tyler, Max ; Chan, Susan ; Leach, Jonathan. / 5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager. 2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2019. pp. 106-108 (International Solid- State Circuits Conference (ISSCC)).
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abstract = "Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to laser returns affected by the inverse square law over 2-3 decades of distance, diverse target reflectivity, and high solar background [1]. Integrated CMOS SPADs have a native DR exceeding 140dB, typically extending from the noise floor of few cps to 100's Mcps peak rate. To deliver this DR to downstream DSP, large SPAD time-resolved imaging arrays must count and time billions of single photon events per second demanding massively parallel on-chip pixel processing to achieve practical I/O power consumption and data rates. Hybrid Cu-Cu bonding offers a mass-manufacturable platform to implement these sensors by providing high-fill-factor SPADs optimised for NIR stacked on dense nanoscale digital processors [2]. Stacked sensor architectures involving pixel-level histogramming, on-chip peak detection and TDC/processor resource sharing are now being investigated [3-5].",
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Henderson, RK, Johnston, N, Hutchings, SW, Gyongy, I, Abbas, TA, Dutton, N, Tyler, M, Chan, S & Leach, J 2019, 5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager. in 2019 IEEE International Solid-State Circuits Conference (ISSCC). International Solid- State Circuits Conference (ISSCC), IEEE, pp. 106-108, 2019 IEEE International Solid-State Circuits Conference, San Francisco, United States, 17/02/19. https://doi.org/10.1109/ISSCC.2019.8662355

5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager. / Henderson, Robert K.; Johnston, Nick; Hutchings, Sam W.; Gyongy, Istvan; Abbas, Tarek Al; Dutton, Neale; Tyler, Max; Chan, Susan; Leach, Jonathan.

2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2019. p. 106-108 (International Solid- State Circuits Conference (ISSCC)).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Abbas, Tarek Al

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AU - Chan, Susan

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Henderson RK, Johnston N, Hutchings SW, Gyongy I, Abbas TA, Dutton N et al. 5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager. In 2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE. 2019. p. 106-108. (International Solid- State Circuits Conference (ISSCC)). https://doi.org/10.1109/ISSCC.2019.8662355