Open dataset for "A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs" in DLMCS 2016

Rob Stewart (Creator)

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2016
A Dataflow IR for memory efficient RIPL compilation to FPGAs
Stewart, R., Michaelson, G. J., Bhowmik, D., Garcia, P. & Wallace, A., 2016, Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings. Springer, p. 174-188 15 p. (Lecture Notes in Computer Science; vol. 10049).
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