Research Output per year
RIPL and C++ source code, results data and images for"A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs" which was published in DLMCS 2016.
|Date made available||22 Feb 2017|
Stewart, R., Michaelson, G. J., Bhowmik, D., Garcia, P. & Wallace, A., 2016, Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings. Springer International Publishing, p. 174-188 15 p. (Lecture Notes in Computer Science; vol. 10049).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Stewart, R. (Creator) (22 Feb 2017). Open dataset for "A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs" in DLMCS 2016. Heriot-Watt University. DLMCS2016_open_data(.zip). 10.17861/283859ba-f53b-40b9-8202-2ee4e302bc0f