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Open access dataset for "Verifying Parallel Dataflow Transformations with Model Checking and its Application to FPGAs"
Rob Stewart
(Creator)
School of Mathematical & Computer Sciences
Computer Science
Dataset
Overview
Research output
(1)
Description
This article has been accepted to the Elsevier Journal of Systems Architecture.
Date made available
10 Sept 2019
Publisher
Heriot-Watt University
Contact
[email protected]
DOI
10.17861/85ff96b4-2c6b-4f58-8322-74f0ab45f684
Research output
Research output per year
2019
2019
2019
1
Article
Research output per year
Research output per year
Verifying Parallel Dataflow Transformations with Model Checking and its Application to FPGAs
Stewart, R.
, Berthomieu, B., Garcia, P.,
Ibrahim, I.
,
Michaelson, G.
&
Wallace, A.
,
Dec 2019
,
In:
Journal of Systems Architecture.
101
, 101657.
Research output
:
Contribution to journal
›
Article
›
peer-review
Open Access
File
Linear Temporal Logic
100%
Model Checking
100%
Field Programmable Gate Arrays
100%
applications
100%
transformations
100%
7
Link opens in a new tab
Citations (Scopus)
229
Downloads (Pure)
Cite this
DataSetCite
Stewart, R. J. (Creator) (
10 Sept 2019
). Open access dataset for "Verifying Parallel Dataflow Transformations with Model Checking and its Application to FPGAs". Heriot-Watt University.
10.17861/85ff96b4-2c6b-4f58-8322-74f0ab45f684